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Test Definitions


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Pacer Clock
  An on-board or external timing source that sets the timing for events such as analog-to-digital and digital-to-analog conversions.
Source: Measurement Computing
  The material that surrounds the die or chip (in an Integrated Circuit). The package protects the electronic circuitry.
Source: Xilinx
  An element that packs a steam of bits into a stream of bytes.
Source: Datacube
  A basic message unit for communication across a network. A packet usually includes routing information, data, and (sometimes) error detection information.
Source: Xilinx
Packet Switching
  Packet switching technologies are based on end stations collecting data to be transmitted into packets. Packets may be variable in length or may be of a fixed size, as in ATM. Packets may be transmitted at any time without the setup of a connection with the destination. It is up to the network to determine how to route the data to the destination. At the same time the network does not guarantee delivery and it is up to the end stations to provide mechanisms for reliable delivery. Most data communications technologies are based on packet switching. The use of packet switching is driven by the underlying assumption that computer data traffic is inherently bursty in nature, and not time-critical.
Source: Xilinx
  An area of metalization on a substrate used for probing or to connect to a via, plated through-hole, or an external interconnect.
Source: Maxfield & Montrose Interactive Inc.
  The portion of the conductive pattern on printed circuits designated for the mounting or attachment of components. Also called land.
Source: PCB Universe
Pad Grid Array
  (PGA) - Similar to a pin grid array. An IC package that has solderable connections in a grid layout on the bottom of the package, and is soldered to the surface of the substrate (PWB) with butt solder joints.
Source: Surface Mount Technology Association
  A special flavor of circuit board used for high-reliability military applications. Distinguished by the fact that the outer surfaces of the board have pads but no tracks. Signal layers are only created on the inner planes, and tracks are connected to the surface pads by vias.
Source: Maxfield & Montrose Interactive Inc.
  rectangular sheet of base material or metal-clad material of predetermined size that is used for the processing of printed boards and, when required, one or more test coupons.
Source: PCB Universe
Par Meter
  A peak-to-average ratio meter (Par meter) is a device used to measure the ratio of the peak power level to the time-averaged power level in a circuit. This quantity is known as the peak-to-average ratio (p/a r). Such meters are used as a quick means to identify degraded telephone channels. Par meters are very sensitive to envelope delay distortion. They may also be used for idle channel noise, nonlinear distortion, and amplitude-distortion measurements. The peak-to-average ratio can be determined for many signal parameters, such as voltage, current, power, frequency, and phase.
Source: Wikipedia
Parallel Cable III
  The Xilinx Parallel Cable III is a download cable connected to the parallel port of the PC. It is used to program Xilinx FPGAs and CPLDs using the JTAG interface.
Source: Xilinx
Parallel Functional Test Systems
  A cost-effective solution that can test thousands of ICs simultaneously and can provide traditional burn-in as well. This allows semiconductor manufacturers to use their higher cost testers for the high speed and high accuracy tests for which they are best suited, rather than inefficiently using them for time-consuming functional tests.
Source: AEHR Test Systems
Parallel In Serial Out
  (PISO) - Refers to a shift register in which the data is loaded in parallel and read out serially.
Source: Maxfield & Montrose Interactive Inc.
Parallel Poll
  The process of polling all configured devices at once and reading a composite poll response. See also serial poll.
Source: National Instruments
Parallel Scan
  The architectural support of multiple scan chains, that are designed to be used simultaneously, to reduce the number of shift clocks (shift bit depth) involved with the scan process by parallelizing the scan bit depth across several tester channels. This architecture reduces the required clock cycles needed to load a state in the design unit and reduces one aspect of the cost-of-test.
Source: Inovys
Parallel Test
  Testing more than one device simultaneously. By convention, this is usually assumed to be identical tests on identical devices. (contrast to Concurrent Test).
Source: NP Test
Parametric Design Marginalities
  A yield loss mechanism in high-performance products that are caused by either process fluctuations or environmental factors (such as supply voltage or temperature).
Source: Wikipedia
Parametric Fault
  A group of faults that are caused by variations in component parameter values produced by process or environmental changes.
Source: ATE World
Parametric Test
  The measurement and verification of terminal voltage and current characteristics at a device pin.
Source: ATE World
  A form of testing where the voltages, currents, and timing are measured for compliance against specified values.
Source: Hebrew University of Jerusalem "DFT & JTAG" Course
Parasitic Capacitance
  The capacitive leakage across a component such as a resistor, inductor, filter, isolation transformer, or optical isolator that adversely affects high-frequency performance.
Source: eEngineer

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